A wide variety of optical circuits can be realized as a photonic integrated circuit (PIC) on a silicon or dielectric substrate. However, both photodetectors and light emitting devices (lasers, SOAs) are not readily available in a dielectric-based PIC. It is also not possible to realize efficient light emitting devices within a silicon-based PIC.
To equip a dielectric-based or silicon-based PIC with a photodetector, a light source or a similar photonic device, this photonic device is therefore manufactured separately on a different type of substrate as a flip-chip photonic chip (FCPC). When this chip is mounted onto the PIC, a first waveguide of the FCPC is coupled to a second waveguide of the PIC to make an optical connection between the two devices.
Due to the small cross-section of integrated photonic waveguides, the coupling between a PIC and a FCPC requires micrometer to sub-micrometer precision in their relative alignment. The efficiency of the coupling is quantified by the relation between the power of the light before the coupling (in the transmitting device) and after the coupling (in the receiving device). To achieve a good coupling between the two devices, they have to be positioned such that the beam sent by the transmitting device spatially matches the required field profile at the receiving device. Quantitatively, the overlap integral between the two has to be maximized.
Several assembly technologies have been utilized to couple a semiconductor laser to a PIC. In one assembly technology, the laser chip is prepackaged in an optical micro-bench or separate housing (laser subassembly) together with additional optical components such as an optical isolator, a ball lens, etc. and coupled to the PIC using fiber optics or by direct attachment of a micro-bench onto the PIC. The attachment process typically requires active alignment, i.e., the laser chip is emitting light into the PIC, the coupled power is measured and the position of the laser micro-bench or fiber modified until the optimum coupling position is found. The laser subassembly or fiber can then be permanently affixed to the PIC. The laser micro-bench or housing is a significant cost factor in this packaging scheme.
In a more cost effective assembly technology, the laser chip is attached directly onto the PIC chip using a flip-chip process (and is thus a flip-chipped photonic chip—FCPC). Here, the light is coupled directly from a waveguide of the laser chip (the laser stripe) to a waveguide of the PIC chip by being transmitted first through an edge facet of the laser chip and then through a facet of the PIC chip. The facet of the PIC chip can be fabricated by etching into the PIC, wherein a sidewall of the etch then forms the facet. The same assembly technology is used to assemble waveguide photodetectors on PIC chips, where the light is directly coupled from the PIC chip to the waveguide of the photodetector by being first transmitted through a facet of the PIC and then through an edge facet of the photodiode chip. Similarly, a semiconductor optical amplifier (SOA) can be flip-chipped onto a PIC, wherein light is first transmitted from a first PIC waveguide to the SOA and then from the SOA to a second PIC waveguide.
Waveguides on the FCPC and on the PIC can be simply terminated at the facet or slightly before the facet of the respective chip, thus forming a simple edge coupler. They can also be connected to edge couplers facilitating the coupling by expanding the mode size of the waveguides and thus relaxing the alignment tolerances. Such edge couplers can take the form of a taper, wherein the width of the waveguide is widened near the edge of the chip so as to broaden the mode profile, or the form of an inverse taper, wherein the width of the waveguide is reduced well below the single mode condition, reducing the optical confinement and increasing the mode dimensions both in the horizontal and vertical dimensions. Such edge couplers are well known in the art, for example from (V. R. Almeida, R. R. Panepucci, and M. Lipson, “Nanotaper for compact mode conversion,” Opt. Lett. 28(15), 1302-1304 (2003)). In a more advanced edge coupler configuration, several inverse tapers can be merged and tapered down to a unique single mode waveguide, as is known from (N. Hatori, T. Shimizu, M. Okano, M. Ishizaka, T. Yamamoto, Y. Urino, M. Mori, T. Nakamura, Y. Arakawa, “A Hybrid Integrated Light Source on a Silicon Platform Using a Trident Spot-Size Converter,” J. Lightwave Tech. 32(7), 1329-1336 (2014)). Edge couplers receiving a beam and coupling the light to more than one single mode waveguide, wherein such edge couplers have improved alignment tolerances relative to comparable edge couplers coupling the light to a unique single mode waveguide, are further known, for example from (S. Romero-Garcia, B. Marzban, F. Merget, B. Shen, J. Witzens, “Edge Couplers With Relaxed Alignment Tolerance for Pick-and-Place Hybrid Integration of III-V Lasers With SOI Waveguides,” J. Sel. Top. Quant. Electron. 20(4), 8200611 (2014)).
Waveguides are formed by a core material, in which core material the light is guided, and one or more (optical) cladding materials with a lower refractive index, which cladding materials are arranged around the core material. Waveguides can for example be formed by fully or partially etching a higher refractive index thin film (the core layer) located on a lower refractive index material (forming the lower cladding layer), wherein an additional lower refractive index material can be deposited directly onto and around the higher refractive index core material after patterning of the core layer (forming the upper cladding layer). The edge couplers can be defined in the same core layer as the waveguides. In the case of a chip comprising active light-emitting devices such as lasers or SOAs, the core layer comprises light emitting structures such as quantum wells, quantum dots or quantum dashes. Such light emitting structures are formed by interleaving one or several very thin light emitting layers (the quantum wells, quantum dot layers or quantum dash layers) with electrical cladding layers. The very thin light emitting layers are typically thin enough to quantize the free electrical carrier wave functions and have a thickness on the order of a few nm. This thickness is too small to be resolved by the optical field, so that the latter sees an effective medium with an index corresponding to the average of the materials (light emitting layers and electrical cladding layers) weighted with the optical field strength. For this reason the entire stack of light emitting layers and electrical cladding layers is considered part of the (optical) core layer confining the light. The averaged index of the (optical) core layer remains higher than the refractive index of the (optical) cladding layers. Typically, the refractive index of the electrical cladding layer (that is part of the core layer) is also higher than the refractive index of the cladding layers. Waveguides on the PIC or the FCPC are preferentially designed to guide radiation (light) with frequencies between 30 and 1200 THz, wherein radiation with power at one or several said frequencies is transmitted in between the PIC and the FCPC. Typical thicknesses of the core layers on the PIC and FCPC range from 50 nm to 5 μm. Moreover, typical core layer thicknesses for devices at telecommunications wavelengths (C-band, L-band, O-band) range from 100 nm to 3 μm.
The waveguide mode of FCPCs comprising devices such as semiconductor lasers, SOAs or photodetectors can be several microns below the surface of the FCPC. For this reason, a cavity has to be typically etched into the PIC, in which cavity the photonic chip is subsequently flip-chipped. The depth of the cavity then determines the vertical alignment between the edge coupler on the FCPC and the edge coupler on the PIC, said depth thus being critical to enable good optical coupling. Such a flip-chip attachment method is for example known from (M. Kapulainen, S. Ylinen, T. Aalto, M. Harjanne, K. Solehmainen, J. Ollila, and V. Vilokkinen, “Hybrid Integration of InP Lasers with SOI Waveguides Using Thermocompression Bonding,” Proc. 5th IEEE Int. Conf. on Group IV Photon., 61-63 (2008)). In this method, the top metallization layer of an active FCPC such as a laser, SOA or photodetector is in mechanical contact with the PIC or with adhesive layers deposited on the PIC.
An important drawback of this attachment method is that it is sensitive to thickness variations of the top metallization layer of the FCPC, as well as to thickness variations of additional adhesive materials placed, dispensed or deposited between the FCPC and the PIC. Since such thicknesses are typically ill controlled, respectively hard to precisely control, vertical alignment is challenging. For example, the exact thickness of metal electrodes defined by lift-off on laser diodes, SOAs or photodetectors are typically not specified and controlled by manufacturers of standard commercial components. The shrinkage of adhesives or micro-bumps also makes their height very hard to control with sufficient accuracy. A further drawback of this attachment method is that individual dust particles trapped between the PIC and the FCPC can very significantly deteriorate the vertical alignment.
In an improved flip-chip integration scheme, also known in the art from (T. Shimizu, N. Hatori, M. Okano, M. Ishizaka, Y. Urino, T. Yamamoto, M. Mori, T. Nakamura, Y. Arakawa, “Multichannel and high-density hybrid light source with a laser diode array on a silicon optical waveguide platform for interchip optical interconnection,” Photon. Res. 2(3), A19-A24 (2014)), pedestals are fabricated inside the etched cavity, for example by not etching such pedestals while etching the rest of the cavity (e.g., with a masked etch following a lithography step), or by etching such pedestals to a lesser extent than the rest of the cavity. These pedestals are special support structures fabricated on the PIC device to predetermine the vertical position of the FCPC edge coupler with respect to the vertical position of the PIC edge coupler. The mechanical contact only occurs between the pedestal and the FCPC. This has several advantages: For example, the adhesive material can be dispensed only in locations at the bottom of the cavity that are etched to a higher extent, in which case the vertical alignment is not a function of the amount of dispensed adhesive. The same holds for other attachment schemes such as bump bonding, in which case the bump bonds are placed at locations at the bottom of the cavity. The vertical alignment is then also defined by the point contact(s) between pedestal(s) and FCPC and not by the bump bonds themselves. Shrinkage of the bump bonds or of the adhesive merely firmly holds the FCPC in mechanical contact with the pedestals. A further advantage is that this attachment method is much more tolerant to dust, as the actual mechanical contacts only cover a reduced portion of the total FCPC footprint and dust located elsewhere than on the top of the pedestals is unlikely to impact the vertical alignment. In order to provide electrical connectivity to the top surface of the FCPC (which is facing down in the final assembly), metal lanes, metal pads or metal surfaces can be defined at the bottom of the cavity. Conductive adhesives or bump bonds can then further provide electrical connectivity between the metal surface(s) at the bottom of the cavity and electrodes on the top surface of the FCPC.
Even this improved flip-chip integration scheme still has drawbacks, in that even the tops of the pedestals need to be etched by a significant amount (on the order of the cumulative thickness of the top cladding layers of the PIC and the top cladding layers of the FCPC). The variability of this etch is sufficient to substantially impact the vertical alignment accuracy. While the pedestals are etched to a lesser amount than the rest of the cavity, the top of the pedestals still typically needs to be etched by several microns relative to the top surface of the PIC. For example, for a typical laser diode chip the core of the laser waveguide is buried 3 μm underneath the surface. Thus, the top of the pedestals has to be etched 3 μm into the PIC substrate, assuming the PIC waveguide to be at the surface of the PIC. If the PIC waveguide is buried below a top cladding (typically 2-5 μm) the etching of the pedestals has to be even deeper, accordingly. Typical process variations during the deposition of thick layers or deep etching is up to 10%, i.e., the final vertical position of the FCPC edge coupler after assembly can vary by several hundreds of nanometers. Thus, in order to overcome this variability, the fabrication processes have to be extremely well controlled.